logo
 
 Main Menu
 Tutorials
 Forum
 Themes

(6 themes)
 Who's Online
5 user(s) are online

Members: 0
Guests: 5

more...
 Top Posters
1
jgrad
303
2
ebrunvand
61
3 svchw 47
4 ucgrad 35
5
jbakos
34
6
jamesstine
32
7
ekalenda
27
8 pepet 25
9 ashkan2000 20
10 tikkir 20
 Welcome!

Welcome to chiptalk.org!

This is a community site to exchange ideas, discuss problems, and post tutorials about IC design and EDA design tools. This site is non-commercial and is maintained by Johannes Grad and James E. Stine.

This site is also the support page for the OSU Design Flows for MOSIS SCMOS and FreePDK 45nm Variation-Aware Technology. Also, check out the new Wiki. In the coming months we may move many of the tutorials to the Wiki to allow users to contribuite back within the tutorials.

Have a question? Want to chat? Post it in the Forum!
Have something to announce? Something cool on the web? Post it in News!
Want to share knowledge? Post an article in the Tutorials!
Want to promote your site? Found a cool site? Add a link in Web Links!
Want to share a file? Add an entry to the Downloads!
Have some time to kill? Read today's Comics!

For an introduction, please visit the Getting Started Guide.

Sometimes creating an user account doesn't work right. If that happens, please email jgrad@chiptalk.org or james.stine@okstate.edu to have an account created.

 Recent Replied Topics
Forum Topic Replies Views Last Post
Cadence I cannot initiate abstract generator 1 221 6/30 12:57:31
ekalenda 
Cadence I cannot extract the layout 6 612 6/28 12:57:22
erpnjohari 
OSU Cell Library scan cell 2 563 6/28 2:59:14
Urban 
Cadence About GCELLGRID and TRACK statement 1 145 6/27 13:52:01
erpnjohari 
Cadence Encounter & Nangate - Clock Tree Spice Extraction - CDB Files? 1 139 6/27 13:44:27
erpnjohari 
OSU Cell Library pad frame 2 173 6/26 13:31:43
erpnjohari 
Cadence How create a component on Cadence just with his spice parameters? 1 240 6/26 1:41:46
Urban 
NCSU CDK FreePDK45 installation problem 0 341 6/9 9:38:01
zb8521 
Cadence signalstorm library characterization 0 350 6/5 8:29:46
spendela 
Cadence RTL Compiler 15 4672 6/4 1:43:51
achiranshu 
Synopsys Filler Cell 4 890 5/30 4:29:10
mrityunjay 
Synopsys Astro Standerd cell preperation 4 966 5/30 4:26:24
mrityunjay 
Synopsys Astro VHDL netlist input 0 418 5/30 3:59:49
mrityunjay 
OSU Cell Library OA22 translation of osu_soc_v2.7 1 1194 5/27 8:26:33
olivergt 
OSU Cell Library Streaming in gds files 1 575 5/26 23:56:31
erpnjohari 
 Recent News
 Login
Username:

Password:

Remember me

Secure Login
Lost Password?

Register now!

 Search

Advanced Search

 Polls
Is Asynchronous Logic here to stay?
Yes
No

 Headlines

EETimes News
EE Times Semiconductor News

Yahoo Semiconductor News
Yahoo! News

EDA Cafe Industry News

CAD Wire EDA News
CADwire.net


Powered by XOOPS 2.0 © 2001-2003 The XOOPS Project