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The time now is 2013/5/18 6:51
You last visited: 2013/5/18 6:51:40
Total Topics: 414 | Total Posts: 1168
You last visited: 2013/5/18 6:51:40
Total Topics: 414 | Total Posts: 1168
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EDA Tools |
| Forum | Topics | Posts | Last Post | |
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Magic
(RSS)
Talk about the Layout Editor Magic Moderator: jgrad jamesstine |
8 | 14 | 2010/2/9 11:27 Leandro |
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Cadence
(RSS)
A forum to discuss issues with any of the tools by Cadence Design Systems Moderator: jamesstine jgrad |
232 | 746 | 2011/9/24 20:13 Anonymous |
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Synopsys
(RSS)
A forum to discuss any of the tools by Synopsys Moderator: jamesstine jgrad |
23 | 63 | 2011/7/13 8:48 sampham |
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Irsim
(RSS)
Discuss here any issues with the freeware switch-level simulator Irsim Moderator: jamesstine jgrad |
2 | 4 | 2005/10/3 3:06 dinesh |
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Sue
(RSS)
Discuss here the freeware schematic editor Sue, formerly a tool sold my Micromagic. Moderator: jamesstine jgrad |
2 | 3 | 2005/11/15 15:36 jgrad |
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Gemini
(RSS)
Discussion board for the freeware LVS tool gemini Moderator: jamesstine jgrad |
1 | 1 | 2005/8/7 20:31 jgrad |
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NCSU CDK
(RSS)
Discussion board for the NCSU CDK, which provides MOSIS SCMOS rules for Cadence Virtuoso. Moderator: jamesstine jgrad |
65 | 166 | 2011/7/26 13:30 legolas |
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Commercial PDK
(RSS)
Discuss here any issues with commercial PDKs Moderator: jamesstine jgrad |
5 | 6 | 2011/7/5 15:50 Mashhood |
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General Discussions |
| Forum | Topics | Posts | Last Post | |
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EDA Industry
(RSS)
A forum to discuss the EDA industry in general Moderator: jamesstine jgrad |
8 | 9 | 2009/8/3 7:09 pPawlicki |
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Chiptalk.org
(RSS)
A forum to discuss this website and propose improvements Moderator: jamesstine jgrad |
11 | 17 | 2008/5/14 5:42 jojolucky |
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Meet And Greet
(RSS)
Meet and greet for Chiptalk.org members. Get to know your colleagues... Moderator: jamesstine jgrad |
6 | 21 | 2011/4/27 5:34 SteveWolly |
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Unix Users
(RSS)
Unix users tips, questions and solutions |
2 | 2 | 2005/11/16 10:25 jgrad |
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Cell Libraries |
| Forum | Topics | Posts | Last Post | |
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OSU Cell Library
(RSS)
A forum to discuss any issues with the OSU cell library (formerly the IIT cell library) Moderator: jamesstine jgrad |
33 | 92 | 2011/7/15 9:32 mcjohnso |
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Commercial libraries
(RSS)
A forum to discuss commercial standard cell libraries Moderator: jamesstine jgrad |
2 | 3 | 2007/6/13 5:01 jamesstine |
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Chip Design |
| Forum | Topics | Posts | Last Post | |
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Verilog
(RSS)
Discussion board for general Verilog code questions Moderator: jamesstine jgrad |
1 | 1 | 2005/8/7 20:37 jgrad |
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VHDL
(RSS)
Discussion board for general VHDL questions and issues Moderator: jamesstine jgrad |
4 | 6 | 2008/4/5 18:26 don |
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Synthesis
(RSS)
A discussion board for general questions related to logic synthesis Moderator: jamesstine jgrad |
3 | 5 | 2006/5/1 13:59 ebrunvand |
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6 | 9 | 2011/3/1 12:01 rod_pro |
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