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    <title>www.chiptalk.org :: Forum</title>
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    <description>Discuss the EDA Industry, Chip Design and Cell Libraries :: XOOPS Community Bulletin Board</description>
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      <title>VT Cell Library Synthesis [by legolas]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=431&amp;forum=11</link>
      <description>NCSU CDK:: VT Cell Library Synthesis&lt;br /&gt;
Hi,&lt;br /&gt;&lt;br /&gt;Even though the Verilog code has always@(posedge) statements, it is getting synthesized into muxes and not latches.&lt;br /&gt;&lt;br /&gt;How to make sure they synthesize into latches.</description>
      <pubDate>Tue, 26 Jul 2011 13:30:58 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=431&amp;forum=11</guid>
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      <title>Re: Trouble with DRC in NCSU CDK 1.6.0 beta [by legolas]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=310&amp;forum=11</link>
      <description>NCSU CDK:: Trouble with DRC in NCSU CDK 1.6.0 beta&lt;br /&gt;
Hi,&lt;br /&gt;&lt;br /&gt;I was also unable to find the  *.rul files. They were linked to a non-existent location in the NCSU CDK 1.6 beta.&lt;br /&gt;&lt;br /&gt;The *.rul files are all in the &amp;#039;techfiles&amp;#039; folder. You have to link the files in all the other library directories to these files (using the ln-s command).</description>
      <pubDate>Thu, 21 Jul 2011 11:29:14 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=310&amp;forum=11</guid>
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      <title>Re: CDB2OA in Cadence for VT Cell Libraries [by legolas]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=427&amp;forum=11</link>
      <description>NCSU CDK:: CDB2OA in Cadence for VT Cell Libraries&lt;br /&gt;
I think I have been able to resolve the issue for now.&lt;br /&gt;&lt;br /&gt;The steps to do the same are following:&lt;br /&gt;&lt;br /&gt;Create a separate folder say convert:&lt;br /&gt;&lt;br /&gt;&amp;gt; mkdir convert&lt;br /&gt;&amp;gt; cd convert&lt;br /&gt;&amp;gt; mkdir cdb&lt;br /&gt;&amp;gt; cd cdb&lt;br /&gt;&amp;gt; vi cds.lib &lt;br /&gt;&lt;br /&gt;Copy the contents of your previous cds.lib. This cds.lib must also have paths to the NCSU Library that the vtvt standard cell library requires.&lt;br /&gt;&lt;br /&gt;&amp;gt; cd .. (Come back to the convert directory)&lt;br /&gt;&lt;br /&gt;Now in CIW-&amp;gt;Tools-&amp;gt;Conversion Tool Box-&amp;gt;CDB TO Open Access ...&lt;br /&gt;&lt;br /&gt;It will ask for a cds.lib, give the path of the cds.lib present in directory cdb.&lt;br /&gt;&lt;br /&gt;The contents to convert are the vt standard cell libraries as well the NCSU library that these refer to.&lt;br /&gt;&lt;br /&gt;If the above steps are followed the error in the previous post will not figure up.</description>
      <pubDate>Fri, 15 Jul 2011 00:15:38 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=427&amp;forum=11</guid>
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      <title>Re: NCSU CDK 1.6beta, IC v6.1.4, and Spectre simulation with ADE? [by legolas]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=405&amp;forum=11</link>
      <description>NCSU CDK:: NCSU CDK 1.6beta, IC v6.1.4, and Spectre simulation with ADE?&lt;br /&gt;
Hi,&lt;br /&gt;&lt;br /&gt;I am trying to use the NCSU CDK 1.6 beta with the VTVT kit for digital design.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;The VTVT kit asks to copy a divaDRC.rul file in the NCSU kit.&lt;br /&gt;but when I checked in NCSU kit library files all the .rul files such as divaDRC.rul files are marked in red and seem to be corrupted, they cannot be replaced.&lt;br /&gt;&lt;br /&gt;when I run the following command&lt;br /&gt;&amp;gt; ll *.rul&lt;br /&gt;lrwxrwxrwx 1 3339 108 49 Jul  9 16:01 divaDRC.rul -&amp;gt; /local/home/wdavis/NCSU_CDK//techfile/divaDRC.rul&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;What should I do about this?</description>
      <pubDate>Wed, 13 Jul 2011 01:30:22 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=405&amp;forum=11</guid>
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      <title>Re: NSCU CDK vs foundry PDK [by wrdavis]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=423&amp;forum=11</link>
      <description>NCSU CDK:: NSCU CDK vs foundry PDK&lt;br /&gt;
That depends.  The NCSU CDK is a PDK based on the old lambda rules developed by Carver Mead and Lin Conway in the late 70&amp;#039;s.  These rules were accepted by many foundries, but fell out of fashion after the 180nm node.  So, the answer is yes, but restricted to the 180nm node and larger and only for foundries that accept them.  MOSIS still accepts GDSII designed with these rules for the 180nm node and larger technologies.</description>
      <pubDate>Thu, 23 Jun 2011 07:03:30 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=423&amp;forum=11</guid>
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      <title>NCSU CDK 1.6.0 p2m [by stimm]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=422&amp;forum=11</link>
      <description>NCSU CDK:: NCSU CDK 1.6.0 p2m&lt;br /&gt;
Hi all,&lt;br /&gt;&lt;br /&gt;I downloaded NCSU CDK 1.6.0 yesterday, because I&amp;#039;m looking for a solution to import JPEGs into cadence virtuoso for the use in a layout. But I couldn&amp;#039;t find the menu item IMPORT JPEG. Isn&amp;#039;t it already included?&lt;br /&gt;&lt;br /&gt;Thanks,&lt;br /&gt;stimm</description>
      <pubDate>Thu, 12 May 2011 02:12:40 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=422&amp;forum=11</guid>
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      <title>Help regarding AMI 0.5um library/Cadence (IC6.1.1.64) [by ams]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=409&amp;forum=11</link>
      <description>NCSU CDK:: Help regarding AMI 0.5um library/Cadence (IC6.1.1.64)&lt;br /&gt;
Hi, &lt;br /&gt;&lt;br /&gt;               I have tried converting the AMI 0.5um library from cdb to oa by following tutorial in &lt;a href=&quot;http://www.chiptalk.org/&quot; target=&quot;_blank&quot;&gt;http://www.chiptalk.org/&lt;/a&gt; . But unfortunately that procedure is not working for me. I see no standard cells created in my directory. And i have the following errors, though iam attaching the appropriate technology library. Hope some one could help me fix this.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;ERROR   (CDBOA-402): &amp;lt;path&amp;gt;/master.tag is empty or contains invalid data.&lt;br /&gt;&lt;br /&gt;ERROR   (CDBOA-500): The translation was stopped because technology library      &lt;br /&gt;                     &amp;lt;name&amp;gt; referenced by library &amp;lt;path&amp;gt;/&amp;lt;name&amp;gt; does not exist. &lt;br /&gt;                     Ensure that any technology libraries referenced by the     &lt;br /&gt;                     current library are defined in the cds.lib file and avail  &lt;br /&gt;                     able in OpenAccess at the time they are referenced.&lt;br /&gt;&lt;br /&gt;Regards,&lt;br /&gt;roy</description>
      <pubDate>Sun, 26 Dec 2010 14:26:46 -0600</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=409&amp;forum=11</guid>
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      <title>Re: NCSU CDK 1.6.0.beta for Virtuoso 6.1 [by teresap989]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=242&amp;forum=11</link>
      <description>NCSU CDK:: NCSU CDK 1.6.0.beta for Virtuoso 6.1&lt;br /&gt;
Quote:&lt;div class=&quot;xoopsQuote&quot;&gt;&lt;blockquote&gt;&lt;br /&gt;wrdavis wrote:&lt;br /&gt;Hi all,&lt;br /&gt;&lt;br /&gt;By popular demand, a beta version of the NCSU CDK for OpenAccess and Virtuoso 5.2.51 and 6.1 is now available for download at &lt;a href=&quot;http://www.eda.ncsu.edu&quot; target=&quot;_blank&quot;&gt;http://www.eda.ncsu.edu&lt;/a&gt; (called NCSU CDK 1.6.0.beta).  We&amp;#039;re short of the manpower to fully support this kit at the moment, so we&amp;#039;re hoping that the user community can help us to fix the problems with this release.  Please post problems and solutions to this discussion thread, and in time, we&amp;#039;ll incorporate the changes into another distribution.&lt;br /&gt;&lt;br /&gt;At the moment, thanks to Matt Guthaus at UC Santa Cruz, it appears that layout (with P-Cells) and DRC work.  I think that LVS and Extraction should be working, too, but haven&amp;#039;t had a chance to verify it myself.  Please let me know what kinds of problems you encounter.  Also, please post here, rather than e-mailing me directly, so that we can have a public record of all the issues.&lt;br /&gt;&lt;br /&gt;Best regards,&lt;br /&gt;&lt;br /&gt;Rhett&lt;/blockquote&gt;&lt;/div&gt;&lt;br /&gt;Such a very amazing link! &lt;br /&gt;Thanks you for the post.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;__________________&lt;br /&gt;&lt;a href=&quot;http://moviesonlineworld.com&quot; target=&quot;_blank&quot;&gt;Watch Let Me In Online Free&lt;/a&gt;</description>
      <pubDate>Wed, 29 Sep 2010 02:22:06 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=242&amp;forum=11</guid>
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      <title>ami06 wire bond pads [by sambhav08]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=404&amp;forum=11</link>
      <description>NCSU CDK:: ami06 wire bond pads&lt;br /&gt;
Hi,&lt;br /&gt;&lt;br /&gt;Does anybody know where can i find the wirebond pads for ami06 technology in the ncsu cdk 1.6 beta? I am using cadence IC 6.1&lt;br /&gt;&lt;br /&gt;Also, when you go to the kit download page, which are the packages i am supposed to download and install?&lt;br /&gt;&lt;br /&gt;Thanks,&lt;br /&gt;Sam</description>
      <pubDate>Wed, 12 May 2010 10:31:36 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=404&amp;forum=11</guid>
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      <title>Re: Exporting with Virtuoso 6.1.1 and ncsu...1.6.0 PROBLEM [by vaibhavgar]</title>
      <link>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=400&amp;forum=11</link>
      <description>NCSU CDK:: Exporting with Virtuoso 6.1.1 and ncsu...1.6.0 PROBLEM&lt;br /&gt;
I think I know why this is happening. I am not sure if I have the right idea but it seems that Cadence 6 no longer reads the text .tf file for layer info for exporting or importing. There is a way in cadence to convert old files to the new format. However as a quick fix when you export stream in Cadence 6, in options, under layers tab you can do load file and use the attached file I created for mosis AMI 0.5um layers. You can edit the file for your technology/fab if you know the GDS numbers. If you are using a different process than AMI 0.5um but use mosis, check mosis&amp;#039; site for technology codes/layer codes for the layer mapping. The format is layer_name purpose gds_number stream_datatype. The second and fourth parameter are generally drawing and 0.&lt;br /&gt;&lt;br /&gt;In the first tab of option you can specify viaLayerMap file.  You can then use the new created viaLayerMap file and the file I posted (or the one cadence creates) to import the designs back and check. When you import using viaMap and contacts that you created using the layout macro are not imported back as cells in your library but as macros from the technology library.&lt;br /&gt;&lt;br /&gt;Once done setting the files, click translate and that should be it.&lt;br /&gt;&lt;br /&gt;Hope this helps</description>
      <pubDate>Fri, 2 Apr 2010 07:33:53 -0500</pubDate>
      <guid>http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=400&amp;forum=11</guid>
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