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Names of layers in IBM PDK 9FLP M1 gd, vd, os, ls, pn, ll... [by mmajzoobi]

Thu, 6 Aug 2009 13:03:54 -0700

Commercial PDK:: Names of layers in IBM PDK 9FLP M1 gd, vd, os, ls, pn, ll...
I am a newbie in ASIC design and I do not have much experience in working with design kits. I am currently trying to tape out a chip but working with the tools are having me a hard time. So as a simple exercise I decided to make a chip with single inverter and go through all the steps at once. I have IC 6.1 and Assura installed (+ Hspice ...). My design is targeting IBM 9flp (90nm) technology and I have the design kit integrated into the CIW.

Now, I am about to layout the inverter in the Layout Editor tool but I noticed that there are so many different layers which makes me so confused. For instance for the first metal layer (M1), there are M1-gd, vd, os, ls, pn, ll, vp, on layers (similar variants for other metal layers).

I was wondering what is the difference between these variants/layers? Is there any documentation from IBM for these layers? Could someone give me some insight?

Thanks,
Mehrdad

SCSI and Ethernet Clock Source [by jojolucky]

Thu, 8 May 2008 03:19:54 -0700

Commercial PDK:: SCSI and Ethernet Clock Source
Description

The MK1442/MK1443are the ideal way to generate clocks for desktop computer motherboards and
LAN workstations. Using analog Phase-Locked Loop (PLL) techniques, the devices accept a 14.318 MHz crystal input to produce multiple output clocks up to 100 MHz. They provide 2XCPU, CPU, floppy controller, keyboard, system, SCSI and Ethernet clocks. The MK1442/3 are perfect for new Pentium� Processor, PCI bus and 486 systems. The devices can operate at 5V or 3.3V up to and including 80MHz on the CPU clock.

The devices are identical except the MK1442 has an Output Enable (OE) pin that tri-states all
outputs when taken low, and the MK1443 has an extra 14.318 MHz clock.

Features
� Provides exact frequency Ethernet and SCSI clocks
� 5V or 3.3V (up to 80MHz) operation
� Output clock frequencies up to 100 MHz
� Pentium� Processor compatible timing
� 486 compatible smooth frequency transitions
� Seven or eight output clocks
� Compatible with X86 and 680X0 CPUs
� Skew controlled 2X and 1X CPU to within 250ps
� Packaged in 16 pin skinny SOIC or PDIP
� Duty cycle of 47.5/52.5 up to 66.66 MHz
� Duty cycle of 45/55 up to 100 MHz
� Total of 15 different selectable CPU frequencies
� Tri-state outputs for board level testing
� 25mA drive capability at TTL levels
� Keyboard frequencies of 12MHz (-01), 8MHz (-02), or 16MHz (-03)
� Advanced, low power CMOS process
� MK1442 - output enable
� MK1443 - two 14.318 MHz outputs

Block Diagram

Non-linear Poly-2 Resistor in CMOS 0.35um VIS(Vanguard-TSMC) [by gte558w]

Mon, 7 Apr 2008 11:37:40 -0700

Commercial PDK:: Non-linear Poly-2 Resistor in CMOS 0.35um VIS(Vanguard-TSMC)
We recently did some designs with CMOS 0.35um VIS (Vanguard-TSMC) process. The poly-2 resistors came out very non-linear with 10-100x variations from the design values. We used ICartis for this wafer run.

We are suspecting that we made a change in the poly-2 resistors from 50ohm/sq to 2kohm/sq in the design kit as intructed by ICartis. Not sure, if this could be the issue or simply the run was bad. Although, VIS (vanguard) did test their own test resistors which came good.

Has anyone seen something like this before.

Thanks,
Shakeel

PDK Vender let you down? [by jgrad]

Sun, 7 Aug 2005 18:33:19 -0700

Commercial PDK:: PDK Vender let you down?
PDKs are often very powerful, but also hard to use. And support may not always be great. Just post an item here and we will see what we can do.