All

I just finished importing my design into cadence encounter. Now I want to estimate the delays between two given nodes, say, between the two registers that are used in the design.

I tried looking into Timing -> Calculate Delay, and it generates a .sdf file, which looks something like this:



(DELAYFILE
(SDFVERSION "OVI 3.0")
(DESIGN "ModCounter")
(DATE "Sat Sep 6 03:59:12 2008")
(VENDOR "Silicon Perspective, A Cadence Company")
(PROGRAM "First Encounter SignalStorm Delay Engine")
(VERSION "V1.0")
(DIVIDER /)
(VOLTAGE 5:5:5)
(PROCESS "1:1:1")
(TEMPERATURE 25:25:25)
(TIMESCALE 1ns)

(CELL
(CELLTYPE "ModCounter")
(INSTANCE )
(DELAY
(ABSOLUTE
(INTERCONNECT data_in[7] MUX/g69/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[7] REG_B/Q_reg_7/D (0:0:0) (0:0:0))
(INTERCONNECT data_in[6] MUX/g79/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[6] REG_B/Q_reg_6/D (0:0:0) (0:0:0))
(INTERCONNECT data_in[5] MUX/g81/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[5] REG_B/Q_reg_5/D (0:0:0) (0:0:0))
(INTERCONNECT data_in[4] MUX/g71/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[4] REG_B/Q_reg_4/D (0:0:0) (0:0:0))
(INTERCONNECT data_in[3] MUX/g77/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[3] REG_B/Q_reg_3/D (0:0:0) (0:0:0))
(INTERCONNECT data_in[2] MUX/g83/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[2] REG_B/Q_reg_2/D (0:0:0) (0:0:0))
(INTERCONNECT data_in[1] MUX/g73/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[1] REG_B/Q_reg_1/D (0:0:0) (0:0:0))
(INTERCONNECT data_in[0] MUX/g75/A (0:0:0) (0:0:0))
(INTERCONNECT data_in[0] REG_B/Q_reg_0/D (0:0:0) (0:0:0))
(INTERCONNECT clock clock__L1_I0/A (0:0:0) (0:0:0))
(INTERCONNECT control MUX/g69/B (0.0078:0.0078:0.0078) (0.0078:0.0078:0.0078))
(INTERCONNECT control MUX/g71/B (0.0088:0.0088:0.0088) (0.0088:0.0088:0.0088))
(INTERCONNECT control MUX/g77/B (0.0087:0.0087:0.0087) (0.0087:0.0087:0.0087))
(INTERCONNECT control MUX/g73/B (0.0085:0.0085:0.0085) (0.0085:0.0085:0.0085))
(INTERCONNECT control MUX/g79/B (0.0098:0.0098:0.0098) (0.0098:0.0098:0.0098))
(INTERCONNECT control MUX/g75/B (0.004:0.004:0.004) (0.004:0.004:0.004))



now, I could not find enough information on how to interpret the files (particularly, the stuff like: (0.004:0.004:0.004).

So, my question is:

a). Can someone please help me understand this file?

b). Is there any way I can generate delay information between two selected points in the circuit? Like between two registers?



Thanks a lot for the help!

Describe your new note here.

Hi

I have a design that has been routed. Does anyone know if there is a way (and how) to extract delays in signal propagation between two different( given) registers?

Thanks.

Dear all,

I would like to know the input impedence of a circuit in CADENCE. I know that it can be a stupid question for you, but for me it's a problem!

Thanks a lot..

All

I generated a _mapped.v (a mapped verilog code) using Cadence Encounter RTL. The trouble starts when I am trying to import this verilog code into Cadence Virtuoso (5.10.41.169, or 2005). I am getting all the views that I need ('schematic', 'functional', and 'symbol') for the sub-modules that make up the top level 'entity' (like 'Generate_only_block_15'), but I get only the 'symbol' and 'functional' views for the top level entity (HanCarlson_Adder).

Can anyone suggest me what could be the reason? Attached is the netlisted .v (_mapped.pdf) file and the CDS.log file (name changed to CDS_log.txt).

Would really really appreciate any thoughts

Thanks a lot!

Attach file:

---

HanCarlson_Adder_mapped.pdf Size: 45.98 KB; Hits: 7
CDS_log.txt Size: 2.48 KB; Hits: 6

In my own cell library, the IO and power/ground ports are all the line labels. I prefer that in the lef file, they are also line label pins. For the signal pins, it works fine by assigning them as line shape pin, but for the power/ground pins, if they are assigned as line shape pins, the SRoute did not route at all and the Vdd and GND are open nets. Even if I change only one cell's power and ground pins to square pins that the SRoute will route normally. But I cannot explain why does it act like that?

In the soce user guide, it only said that "it connect power and ground nets from end-to-end, terminating at the power rings."

I checked the solutions for open nets in soce user guide, it suggested that it might be problems with pins that have hot physical geometry, which I think the line label pin is of this kind. But if it is the problem, then, why does it route correctly with IO line label pins and also with power/ground pins even if there is only one cell containing square power/ground pins?

Can anyone explain the action of SRoute when routing power and ground nets?

Thank you very much!

I used both PKS and RTL compiler to synthesize a verilog file, then used the .v file to do place and route with soc encounter. When I do post-layout simulation, I find that the routing result file using .v file generated by PKS produced the right result, while the one using .v file generated by RTL compiler cannot produce the right result, because the synthesis result from RTL compiler contained:

assign SelExt = IR[15];
assign SelV0 = SelC0;
assign SelZ0 = SelC0;
assign SelZ = SelC;
assign SelV = SelC;

Then after routing, when I do extraction, there are only SelZ, SelZ0 and SelExt signals left, while SelC, SelC0, SelV and SelV0 are deleted as being the same nets, so it caused problems of not matching the IO list of the module when I simulate.

Then I tried with another behavioural design, similarly the routing result using PKS as synthesis tool produced the right result, while the one using RTL compiler failed to pass the simulation. But this time, it did not have the same nets problem, just not being able to produce the right result.

I don't understand. Is that possible that using PKS and RTL compiler synthesize the same design while the files did not have the same function? Or I made mistakes? (I used the same process to do place and route and except the .v file, the two designs have the same other files)

Thank you!

I am migrating an analog design to Cadence 6. It appears that the NCSU CDK 1.6.0 has added some new design rules. For instance:
(SCMOS Rule 11.6) poly2 to unrelated metal1 spacing: 0.60 um

This rule seems to require that no metals be routed over top of ploy2. I can not find any change log or other explanation of the new rule.

Can any one tell me if there is an error in how this rule is written or a reason for why I can't route metal over poly2?

Thanks

Hi, I created a design in VHDL, and then using Cadence Encounter, converted it to a verilog netlist (.v file attached).

I 'import' the .v file in virtuoso, (5.10.41.169, or 2005). Everything goes well, and I get 'schematic' and 'symbol' views of the components (like Generate_only_block_12...). I can simulate the same in virtuoso.

However, I do not get the schematic view for my main module (HanCarlson_Adder). I have a 'symbol' view though. I get the messages which say Verilog definition for module AOI21X1 was not found. Using lib 'OSU_Standard Cells_AMI05' cell 'AOI21X1' view 'symbol' as its symbol.

It is confusing, since the components that were generated correctly (Generate_only_block_12...) use 'AOl21X1' component (see .txt file for messages).

Can someone please tell me what's wrong?

Thanks a lot!

Devendra Rai

Attach file:

---

HanCarlson_Adder_EncounterNetlist.v Size: 12.79 KB; Hits: 11
CDS_Log_Snipper.txt Size: 0.69 KB; Hits: 10

Hey, I've finished the flow using abstract, but I compare the .lef file I get with the one included in the OSU package and they're a little bit different, so I figure I must be missing some steps.

Does anyone know where I can get a good step-by-step tutorial on abstract to generate the .lef file? (even a not-so-good one will do -_^ )

-S

Hi

I created a description of a circuit in VHDL and created a .v and .gds2 file from Encounter. All steps were successfully performed.
When I try to import the .v and .gds2 file in ICFB (File -> Import -> Verilog), I get the following warnings in ICFB (stripped down list):
-----------------------start of list------------------------------------
*WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (fill layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
\w *WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (fill layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
\w *WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (fill layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
\w *WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (fill layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
\w *WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (xor2x1 layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
\w *WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (xor2x1 layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
\w *WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (xor2x1 layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
\w *WARNING* dbiGetHeaderMasterCellView: Failed to open cellView (xor2x1 layout) from lib (OSU_Standard_Cells_AMI05) in 'r' mode because cellview does not exist.
-----------------------------End of list----------------------------------------

I guess, this is the reason I don't see *._sch views in my library manager, which is required for simulation in ICFB.
----------------------------------ICFB Message--------------------------------
ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectreS spice cmos_sch cmos.sch schematic veriloga ahdl" for instance I0 in cell HanCarlson_Adder_DCH.
\o Either add one of these views to: Library: Test Cell: HanCarlson_Adder or modify the view list to contain an existing view.
\o End netlisting Aug 22 19:24:38 2008
---------------------------------------------------------------------------------------
I see that the OSU_Standard_Cell library is correctly recognized by the library manager. Please refer to screenshots attached.

Can someone help?

Thanks!

Attach file:

---

  Library_Path_Editor.png (26.71 KB)


  Library_Property_Viewer.png (14.38 KB)

I had problems when I exported the routing results from soc encounter to Magic.

In the SoC encounter, after verifying the results, I saved the design as GDS, and read it into Magic. But it said that there were instances as control_VIA0 and control_VIA1, which I think were the generated vias instances. But I don't have these vias defined in Magic, so when I read the stream file in Magic, it said that it cannot find the cell control_VIA0 and control_VIA1.

Meanwhile, in the soc encounter, the wires indeed connected to the edge of the cell, but when it was imported into Magic, some wires extended over the edge of the cell, while some did not. I don't know why it happened.

Thanks in advance!



Renee

This is due to the broken links between the TechLibs in ../lib/
and the ../techfile/ directory.

for each technology in the TechLibs the three files divaLVS.rul, divaDRC.rul and dviaEXT.rul should be symobolic links to the files with the same name in the techfile directory.

That does mean that they share the same "Scalable SCMOS" rules.

cheers!

We have installed hspice A-2008.03.-SP1
to use with cadence 6.1.2

(we know this works since it works with schematics from the FreePDK installation)

but for the CDK 1.6. beta the cell views are all hspiceS these views are in the cell DB as well. Adding the hspiceS view to the view list does not work, since there are no hspiceS cell views.

Also copying the library and renaming the hspiceS view to be hspiceD did not work.

The error we get is "..netlisting failed, corrupt netlist file could not descend into cell..."

Thanks

For Cadence 6.1.2 and the FreePDK version 1.2 and Ciranova Pyros 4.2.5

runing on linux RHEL 4 64bit.

we are having the following problem -

Schematic entry works fine but when creating layout with the nmos or pmos cells from the TechLib, cadence virtuoso does a panic crash (segfault) as we put down the part on the canvas.

We also tried this on a 32bit machine and got the same results.

Thanks!

Hi,

In the soc encounter, I inserted and synthesized the clock tree, and do Timing optimization of Post-CTS, and run SRoute, NanoRoute, and then run Timing optimization of Post-Route, but there were still timing violatining paths.

How can I delete them eventually?

Thank you in advance!

Renee

I am a cadence starter and I am trying to study standard cell library systematically. Could anyone please tell me where I can find any good tutorials or examples? Thank you.

Hi,

My pins are on M2, and when I do routing, some pins are connected through vias. I only want to connect standard cells pins with wires, not with vias. Where can I set this option, in lef file or in soc encounter?

Thank you in advance!





Renee

Hello,

I'm having problems with this Relative Object Design in Virtuoso XL layout editor.

How do I disable it for the cells I create? When I add new instances of the cells, I would like to be able to align them using absolute coordinates, but since ROD is on, it is always being placed relative to where it has been referenced. (it looks like it is system handled, so I have no control over it)

I would like to do everything old fashioned, nothing automated. I use the GUI to create and move items, I'm not interested in writing SKILL commands.

Please help.

Thanks.

All,

I just started playing around with Cadence Tools and using the NCSU library (1.5.1).

I am interested in using the digital parts, and simulating circuits, and then perhaps measure parasitics (need to learn this part).

However, I get strange error messages when I pull digital gates from the NCSU digital parts library, and then use either 'stimuli' from Analog Environment, or any of the voltage sources.

My simulator is 'spectre'.

Here is the error log:
------------------------------------------------------------------------------------------
Error found by spectre in 'or2', during circuit read-in
"input.scs" 14: Keyword 'ends' found where a field was expected
"input.scs" 15: Syntax error in specification of 'M5'
"input.scs" 34: Syntax error. Quitting
------------------------------------------------------------------------------------------

I used an 'or2' (OR) gate in the schematic, and 'M5' is one of the transistors used in the 'or2' gate.

Also attached is the snapshot of a level below the 'M5' transistor (Cadence_Below_M5_Snapshot.jpg)

Can someone help?

Thanks!

Attach file:

---

  Cadence_Below_M5_Snapshot.jpg (80.32 KB)

Hello,

I'm new to cadence and would appreciate you help.

I'm trying to generate a layout from my schematic. In virtuoso, I go to Tools>Design Synthesis>Layout XL and generate a new layout. Then in Virtuoso Layout Editing, I go to Design>generate from source. I choose to generate everything.

When done, I can see the instances are generated, however, only one layer is displayed (TRENCH|dg). I don't know if others are also generated for the devices. The LSW window correctly displays all layers available, but only one layer is shown for devices. I

I don't know if I'm not generating of displaying them right.

Can you please help?

Thanks.

Gubidik

Thank you ekalenda
I succeeded to get the files your mentioned.

With a new installation, and the design using the techfile installed with the layerMap file, I would say the techfile and the layerMap are out of sync at your PDK provider. Perhaps they left in the "metal1 drawing" definition but you were supposed to use some other layer? Look at the layerMap file to see if it has layers which seem to have the same meaning, just a different name, and use them instead.

You might also talk to the PDK provider.

In the soc encounter, what should I do if I only want the wire to connect the pins and route only to the edge of the cell. I tried to edit the lef file,and added one statement "NOWIREEXTENSIONATPIN ON ;" , but the wire still extended the cell edge by one-half of the routing width.

How can I solve this problem and connect pins and wire by abutment?

Thanks in advance!

Renee

I've been told by a student that other universities are running NCSU-CDK 1.6.1. Where do I find this version?

Thank you!

John

This is a brand new installation. Any other suggestions?

Thanks!

John

The Info message about the -viaMap option is just that, information. It has nothing to do with the warnings you are getting.

Your design has shapes on layer/purpose pairs which are not defined in the layerMap file. This means the software has no clue what Stream layer number and type to assign to those shapes. As a result, you get the warning and the shapes are ignored.

Since LPPs like "metal1 drawing" are fairly normal, your layerMap file may have been corrupted or incorrectly modified. It is also possible that the layerMap file is correct and someone added LPPs to the techfile which they should not have. Some techfiles use LPPS like "MET1 drawing" instead of "metal1 drawing".