Hello everybody

I encounter today the existantial question of: why cadence gives me negative Cgs ???
From a designeer point of view I need just to know a value for Cgs cdb Cgd, but cadence gives me a lot of parameters that will take me to much time to read the bsim documentation to figure out what they represent
Cgd Cdg cgg Cgs Csg ... etc

has somebody direct formulas that allow to go from cadence parameters to the more friendly Cgs Cgd Cdb capacitances

Thank yiou in advance

Hi everyone

I would like to develop some cells with the Magic VLSI tool and I would like to use the FreePDK 45nm open technology from NCSU.

So I have some questions:

1. Does anyone know where I can find the technology file" (.tech) of the FreePDK 45nm for the Magic VLSI tool?

2. If no such file exists, would be possible to modify "scmos.tech" to adapt to FreePDK? Any tips on how to do this?

Thank you very much for your kind cooperation and excuse me for my bad english.

Hi,

I am now using Cadence 6.1 plus NCSU CDK 1.6 beta package. I fixed some soft links so that I can do LVS, DRC, EXT.

However, I cannot extract netlist from a schematic or a layout in hspiceD simulator. The error msg is saying some thing like that "Cannot find any info on instance "M0"....."

I am wondering if any one encountered the same problem and know how to fix it.

Thanks for any help.

Hello,

I am trying to layout a circuit created using NCSU_Analog_Parts library. The is when I try to automatically create instances sources from the schematics in LayoutXL no devices from this library is actually generated. The LayoutXL software is unable to recognize the layout macros of the technology file attached to the design library.

Please help us with the layout process, thank you.

Quote:

Hi,

There is basic tutorial to use EPS (Encounter Power System) in order to analyze static/dynamic power consumption.
See man for report_power command and tools/share/fe/*
directories within SOC installation hierarchy.

Quote:

Hi,

You need to create LEF/Liberty library files for such blocks to be able to use in digital backend. Also you could create a pure black box specifing black box commands (see man for details) and using subset of floorplan editing commands in way to specify sizes/boxes of such blocks.

Quote:

Hi

See man pages or help for report_timing/timeDesign commands.
It can be applied for asynchrouns design.

Quote:

Hi,

Usually synthesis tools operate on ideal clocks that meaning no delay in a clock path from a clock source to the leaf cells.

It leads in no optimization on clock paths.
Buffers insertion could appear in case when clock path violates for some kind of constraint. For example, it is max fanout, transition time, capacitance or for another reason.

Buffer insertion on clock nets is typically done during clock tree synthesis, but it should be in backend tools.

Quote:

Hi!

It sounds like as you need some one of power analysis tools like VoltageStorm (for pure Cadence digital flow) or PrimeRail or smth else.

Please make the question more clear?
Do you need to measure: power consumption, total current, IR drop, etc?

Hi,

I would like to know how to calculate
dynamic Power
static Power(leakage Power)
in SoC Encounter.
(I am using SoC encounter 8.10)

Please let me know the commands or steps to evaluate the whole power analysis.

Else give me some working links so that i can check and solve my issues.

Thanks,
MaDdY.

Hi James,

Yes, ELC replaced SLC, so once we installed the new package (ETS08) and started using the "elc" command to start the tool everything started working again.

elc appears to be identical in every way to slc, so it's strange that Cadence made this change.

Sorry I forgot to follow-up.

Thanks,
-Jason

Jason,

I believe that SignalStorm was replaced by Encoutner Library Characterizer. Did you check whether you are running this tool? The idea was to integrate into SOC Encounter, so it appears to be a good integration. Let me know if you find any success. I hope all is well. Take care.

James

It seems that the error was not caused by a parser.
It is caused by



I commented out the two functions in opusUnix.il as they seem to be implemented natively now. So, the problem is now resolved. I still need to check if this minor edit would negatively affect older versions of Virtuoso and MMSIM.

It seems that the forum is dead. Anyway thanks for viewing this post 27 times!

Heres the patch enjoy!

Hello everyone.

I haven't tried to use SignalStorm since our last license renewal but now it won't check out a license, while ICFB still works just fine. Did Cadence discontinue shipping the SignalStorm license feature after the change-over to Encounter Library Characterizer?

Also, anyone know what the versityd and verplex daemons are used for? Ours are broken at the moment but I suspect that we don't need them...

Thanks in advance!
-Jason

I have a simple inverter simulation which works fine using IC 6.1.2 and ADE GXL. However, after upgrading to 6.1.3 I get the following error:


cat logs_asd1815/Job0.log



I am still debugging the skill code. I will post my results, if any.
+The simulations work fine with ADE L but not GXL.
+I am using the latest NCSU CDK 1.6.0 beta and MSIM07.11.071.

Hello everyone

does anyone know where I can download the kit NCSU CDK version 1.3 from?, I need it for an old version of Cadence 5.0.33

Thanks,

thank you everyone for the reply

I am a newbie in ASIC design and I do not have much experience in working with design kits. I am currently trying to tape out a chip but working with the tools are having me a hard time. So as a simple exercise I decided to make a chip with single inverter and go through all the steps at once. I have IC 6.1 and Assura installed (+ Hspice ...). My design is targeting IBM 9flp (90nm) technology and I have the design kit integrated into the CIW.

Now, I am about to layout the inverter in the Layout Editor tool but I noticed that there are so many different layers which makes me so confused. For instance for the first metal layer (M1), there are M1-gd, vd, os, ls, pn, ll, vp, on layers (similar variants for other metal layers).

I was wondering what is the difference between these variants/layers? Is there any documentation from IBM for these layers? Could someone give me some insight?

Thanks,
Mehrdad

Subject: HELP! Searching for research participants.

Hi,

my name is Peter, I am a social scientist from Frankfurt, Germany. Right now I am starting the research for my PhD thesis „Engineers and work in global design networks of the semiconductor industry“. I want to study how international teamwork is affecting the work of engineers, what kind of dynamics are being triggered on the level of skill sets and required qualifications. Besides pure analysis I would like to contribute to a better regulation of innovation offshoring in the semiconductor industry.

One idea of the PhD thesis is to compare the situation between engineers in developed countries like Germany, France, USA and engineers in developing countries like the Czech Republic, Romania, Armenia, India and China. As for the developing countries I want to focus mostly on Eastern Europe because it is oftentimes overseen in the academic and public discussions about innovation offshoring.

Methodically my research will focus on interviews with experts – i.e. R&D engineers and IC designers, R&D and project managers, HR managers, academic lecturers and also representatives of professional associations.
As you probably can imagine getting in touch with engineers will be the most difficult task, as going the official way always requires approval of management, who is sometimes not very happy to let the engineers speek with social scientists (at least these are my experiences). This does not mean that I will not try to go the official way, but as groups and forums are an important communication platform for engineers, I decided to also try it through this more informal channel.

The most important thing: ALL INFORMATIONS GATHERED IN MY RESEARCH WILL BE TREATED WITH FULL CONFIDENTIALITY AND WILL BE PUBLISHED ONLY AFTER A THOROUGH ANONYMISATION! NO PERSONAL NAMES OR COMPANY NAMES WILL EVER GET PUBLISHED. This data will also not be used for any commercial use.

I am looking for engineers from semiconductor companies that would be willing to conduct an interview with me (about 1-1,5h). Either through Skype/AIM, or in case I could arrange some interviews from one company I would be very willing to travel.
I am mostly interested in interviewing engineers that work in international design/development teams scattered around the world. In case you do not fit this profile exactly but would be interested in talking with me on this matter, I would be of course interested.
If you know somebody that would be interesting for me, I would be very thankfull if you would forward him my request!

Please feel free to ask further questions!
On request I can provide more information in form of my PhD thesis abstract as well as a interview guide.

Please contact me:
Peter Pawlicki
pawlicki[at]em.uni-frankfurt.de
skype: remigiusch
AIM/ichat: remigjusz

thanks for this one..

commission de surendettement

Hello, hope somebody can help me with this

I export a layout to a cif file using Cadence / PIPO 5.0.0, when importing I get a few warnings and error:

*Warning* invalid cell view -- 167679020
*Warning* invalid cell view -- (unknown)
*Warning* dbGetCellViewDdId: Invalid cell ViewId 167679020
FATAL (101): Failed to create the instance `' of the master cel `pad_frame20'.

where pad_frame20 is the name of the top cell. I noticed that it imports everything except for the corresponding active in ptap and ntap. Any ideas???

about the gds, when I export and import, I do a DRC check of the imported library and everything seems to be fine except for the following errors:

(SCMOS Rule 12.6) transistor electrode to active contact spacing: 0.90 um
(SCMOS Rule 6.2.b) active enclosure of contact: 0.30 um
(SCMOS Rule 6.6.b) active contact to field poly spacing: 0.60 um

again, the active does not seem to be there, and the m1_p1 contacts have errors. Any help would be greatly appreciated.

Thanks,

I'm not really knowledgeable about this matter.
[color=#CCCCCC]sonnerie portable gratuite[/color]

Hi all,
While I am running a Monte-Carlo analysis in Cadence - Spectre, I am receiving the following error.
Couldnt open the file or directory
*/*/veriloga/veriloga.va.ahdlcmi/obj/Linux2.6.18-128.1.6.e15+gcc/optimize/libahdlcmi.so


When I opened the "obj" directory I am able to find the "Linux2.6.18-128.1.6.e15+gcc" directory in it. But I am not able to open it even with all the read, write access.When I try it says no such file or directiry exist. But I can still find the same directory in the obj folder.

How can I overcome this error?

Thanks in advance.

It's helful. Thanks a lot



[color=#EEEEEE]simulationcredit[/color]

Hello everybody,

I have an annoying probleme with EncounterLC ( Signal storm) .
When I run db_spice with the option -keep_log , I can't find the temporary files in encounterlc.work !!!
during the run I can see the folder encounterlc.work , but as soon as db_spice is finished , the work directory is removed !!!
Am I missing to set any environnement variable ???

Many thanks in advance

interesting.. im going to check this one out..
simulation assurance vie

vaibhavgar,
your idea sounds very good, but I'm sorry I can't help with this 'cos I'm not really knowledgeable about this matter.
Good luck
[color=#EEEEEE]simulation credit auto[/color]

Hello All,

I am using allegro (SPB162) to design a RF board , as well as a board for motor control array, using some of TI's chips.

The default installation of allegro come with very few libraries. Are there any libraries for orcad/allegro which has say digikey's parts list or more vendor parts lists than provided?

It seems tools like eagle-pcb have a much better parts list than allegro. However eagle is not as capable.

Any suggestions are welcome..

cheers!

don't forget to turn off the old lic firstly, and then turn on the new lics with the command lmgrd
you can find more options through lmgrd help

I am having troubles typing inside SoC Encounter. All other tools work fine.
i.e. If I select Import design => advanced => power

Then try typing in the power and ground net names it reacts as if I am not typing. While I cannot type there I can paste things into the fields.

I am currently running SoC Ver 7.1 on Red Hat release 5.2

I was wondering if anyone has had the same issue, and if so how was it fixed?

Best
-Steve