Thanks a lot.

Hi,

looking at the map files from the OSU cells is probably the best starting point for your map file. Its a two step process: first you have to find the layer mappings for your process. Then you plug them into the map file, using the OSU ones as examples.

Most likely you already have a GDS map file for Virtuoso, the foundry should have provided one. Or if you have an Assura techfile, you will also find the mappings there. What you will need is a layer number for each metal layer and each via layer.

Here is an excerpt from the OSU cells:


Each metal layer has a similar entry. For MOSIS SCMOS, metal1 has number 49. We put all metal1 routes on that layer. In addition, we also put all the text labels on the metal1 layer (the last two lines). That is actually not legal, since it would mean we wanted to produce the shape of text on the mask. But we use this as a trick to keep the label associated with the correct wire shape. Later in Virtuoso we use the "Create Pins from labels" feature to replace all those labels with actual rectangular pins. I would suggest you give this method of label mapping a try, it works very well, especially when you have pins stacked on different layers on top of each other.

On the Virtuoso side you will need a matching map file for the GDS import. Here is a matching line to the example above:


This means that all entries on GDS layer 49 are placed on "metal1 drawing". Most likely you already have this map file from the foundry. In the rare case where you don't have one, then you are free to make up any map file you want to. As long as you use the same layer numbers on the Encounter and Virtuoso side it will work just fine.

Johannes

How do I create a MAP file for my process so that i can transport my layout from encounter to Virtuoso? I had a look at the one posted at the IIT ASIC design flow tutorial. how do i create a similar one for my process?

Thanks.

Its better we don't post it here or else the spam robots will grab it. You can find it in his member profile (see the top posters list).

I remember James stine telling us about one... could you pass me his mail id. I tried mailing him, it bounced.

Hi,

I don't have any personal experience with free spice tools, but there seems to be quite a number of them out there. The obvious one is probably the well-known Orcad student demo. Since its PCB oriented I think it is akward to use from an IC perspective, but it is easy to install.

Spice Opus looks promising and should run under Windows:
http://www.fe.uni-lj.si/spice/welcome.html

vrmad posted a nice link with freeware MacOS tools. I believe a number of them could be compiled for Linux as well:
http://epicentertech.biz/services/mac_eda/page5.html

In particular TclSpice looks interesting:
http://tclspice.sourceforge.net/

Hope you find something useful. Keep us updated on your experience

Johannes

HI

Well i was confused under which of the forums i should post it.

Is there any free software that works similar to HSPICE.

Vikram

Hi there,

have you checked the Skill User guide and Reference manual? They will probably have the most up-to-date information. You can find the User guide in your IC installation under


and the reference guide under


At IIT in particular you can find all Cadence documentation in a more organized fashion at /import/cadence/doc. The IC documentation is at

There you will find "SKILL Language User Guide.pdf" and "SKILL Language Reference.pdf"

And may this be the last time you have to use Skill
Johannes

Hello,

Can anyone guide me to a detailed cadence skill tutorial

Magic 7 may still be the best layout editor for Mosis SCMOS rules. The OSU library ships with a set of techfiles we converted. The new GDS reader flawlessly reads in Cadence Encounter created GDS files, something Magic 6 wouldn't do.

Tim Edwards (http://bach.ece.jhu.edu/~tim/programs/magic/index.html) has also indicated that as we get smaller in minimum feature size, it may be best not to use Magic. I believe his original post was for 90nm and below.

On the other hand, Magic is a great tool for teaching VLSI and is still useful. Tim does a great job at maintaining the software and giving it great new features for a low price :).

Design Compiler not working? PKS giving you a headache? No problem, post a question here and see what others would suggest.

VHDL is a nice language - with many things that can go wrong. Post a question here, get an answer from a college.

Stumped with a Verilog problem? Simulation not working? Get only X? No problem, post here and see what others have to say.

Commercial library let you down? No problem, just post in this forum.

Any problems with the OSU or IIT cells? Just drop a line in this forum, somebody will know the answer

See anything you would like improved? Like us? Hate us? Feel free to discuss here and get feedback on what others think.

Post anything about the EDA or semiconductor industry in this Forum.

PDKs are often very powerful, but also hard to use. And support may not always be great. Just post an item here and we will see what we can do.

The NCSU kit is a great addition to Virtuoso, allowing SCMOS compatible layout with absolute dimensions. But sometimes things don't work right. No problem, just put a post in this forum!

Any gemini questions? Just post them here. Gemini is a powerful tool, but can be hard to use at times. No problem, somebody out there knows the answer.

Trying to create a schematic in Sue but having problems? Just post your question here

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Simply post any Cadence related items here and we will try to sort it out.

Simply post any Magic related question or issue here and we will try to get an answer.

Depends on which techfile you want to use. For Magic 7 you will need to create many of them using a converter and some manual labor. For Magic 6 all of the classic techfiles are setup. However, most of the sub-180nm techfiles are only created for Magic 7, since it supports those features better than Magic 6.

I want to do some basic layout. Should I go with Magic 6 or Magic 7?