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RTL Compiler
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Hi,

I am wondering if anyone knows any tutorials or examples for RTL Compiler? I'd like to know the exact steps showing the the flow of synthesis, setting design constraints, DFT, etc of RC. Thanks!

Wei

Posted on: 2006/1/19 10:43
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Re: RTL Compiler
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Hi,

I think there are a number of people (including me) who have RC flows they are using but haven't had a chance to make them into a tutorial.

If anybody wants to post a RC tutorial here that would be great Maybe I get a chance to do so eventually.

Johannes

Posted on: 2006/1/19 11:09
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Re: RTL Compiler
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Hi,

I'll post a basic flow for RC at the end of next week, up to and including clock-gating and switching-activity back-annotation for power-driven mapping optimizations. DFT and exporting data for FE will be the second part of the flow.

Nick

Posted on: 2006/1/19 14:13
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Re: RTL Compiler
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Hi Nick,

This is excellent news! I am wondering if you could post it here earlier, that'd be greater... Right now, I am working on a project due in a couple of weeks, and I'd really like to check on important design steps and "bypass" the learning curve of RC as much as possible.

If you have part of the flow written, could you send it to me before it is well done? I really appreciate you help!

my email: svchw AT hotmail DOT com

Wei

Posted on: 2006/1/20 7:28
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Re: RTL Compiler
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Hi,

for what it's worth, here is a script I used the other day to synthesize an adder:


if {[file exists /proc/cpuinfo]} {
  sh grep "model name" /proc/cpuinfo
  sh grep "cpu MHz"    /proc/cpuinfo
}

#* Set up
set DESIGN adder64

set delay1 1000

set SYN_EFF high
set MAP_EFF high

set SYN_PATH "."

set_attribute lib_search_path {../../../share/cdk090/timing} / 
set_attribute hdl_search_path {.} /
#set_attribute wireload_mode <value> /
set_attribute information_level 7 /

set_attribute library slow.lib
#*generates <signal>_reg[<bit_width>] format
#set_attribute hdl_array_naming_style %s\[%d\] /  

read_hdl adder64.v
elaborate $DESIGN

#* Apply Constraints
define_clock   -period $delay1 -name vclk
external_delay -input   0 -clock vclk [find / -port ports_in/*]
external_delay -output  0 -clock vclk [find / -port ports_out/*]

set_attribute external_driver [find [find / -libcell BUFX2] -libpin Y] /designs/adder64/ports_in/*


#ungroup -flatten -all

check_design -unresolved

#* PLE
#set_attribute wireload_mode physical /
#extract_phys_data [-lef <lef_file(s)>] [-captable <cap_table>_file] 

#set_attribute force_wireload <wireload name> "/designs/$DESIGN"

report timing -lint

#*Synthesizing to generic 
synthesize -to_generic -eff $SYN_EFF

#*Synthesizing to gates
synthesize -to_mapped -eff $MAP_EFF -no_incr

#*Incremental Synthesis
synthesize -to_mapped -eff $MAP_EFF -incr   

report timing > timing.rpt
report area   > area.rpt
report gates  > gates.rpt
report power  > power.rpt
write -m  >  ${DESIGN}.mapped.v

write_sdc >  ${DESIGN}.sdc

quit

Posted on: 2006/1/20 7:41
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Re: RTL Compiler
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Johannes,

Thank you so much!

BTW: for pad/IO library characterization, SignalStorm is still the right tool to use, am I right? Thanks!

Wei

Posted on: 2006/1/20 8:04
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Re: RTL Compiler
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Hi,

yes, SLC has worked very well for me with IO cells.

Johannes

Posted on: 2006/1/20 8:09
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Re: RTL Compiler
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Hi,

For the charaterization of IO cells, if there are two possible voltages (e.g. IO=3.3V, core=1.8V), is there a way to set two voltage supplies in the simulation "setup" file?

Also, how to generate input vectors with different voltage levels in SLC? for example, some signals have 3.3V voltage swing...

Thanks!

Wei

Posted on: 2006/1/20 10:47
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Re: RTL Compiler
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Hi,

I figured out something from the SLC manual. Will keep you posted if I have further questions. Thanks!

Wei

Posted on: 2006/1/20 11:11
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SLC IO charaterization
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Hi Johannes,

do you still have the simulation setup file for IO library? I'd like to see how the multi voltage supplies are handled. To be more specific, I'd like to know the setup.ss file and the environment variable settings.

Right now, we are basically following the simulation setup file example for the IO cells in the manual, and setting env vars to include both vdd and vdd3.3 as power supplies. And during simulation, the error is "simulated value mismatch the estimated value", this happens to the gate terminal of a 3.3V PMOS inside the 1.8-to-3.3 level converter. That signal has a transistion R->R, which I am not sure making sense if "R" means rising edge. Maybe I am wrong.

Thanks!

Wei

Posted on: 2006/1/20 13:38
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Re: RTL Compiler
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You may want to take a look at the SLC scripts we used for the AMI05 cells in the OSU library. Those are the only scripts I can publicly share. The example in the SLC manual is pretty complex but should have all the commands necessary to build the characterization flow.

Your eror message seems to indicate a functional problem with the cell. You may want to run that case in Spice to make sure the cells behaves as expected.

Johannes

Posted on: 2006/1/20 16:28
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Re: RTL Compiler
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Hi,

It is possible to setup two different voltage sources as you intend. I don't know what the error you are getting means though. For signal storm, in the setup you can define two different signal types with any names.

Signal IO3.3V{
unit = ABS;
etc...
}
Signal CORE1.8V{
...}

Then you create indices for the input slews, loads, etc.
You also have to create groups for the different pin types, CORE pins, POWER3.3V pins, POWER1.8V pins, PAD pins, etc.

To have both voltage sources available:
set process(typical){
simulation ...
index ...
signal ...
etc.
}
set signal(typical){
Group(POWER3.3V) = IO3.3V;
Group(POWER1.8V) = CORE1.8V;
};

Finally:
set group(typical){
name = PAD;
index = xxxxx;
signal = IO3.3V
}
set group(typical){
name = CORE;
index = xxxxx;
signal = CORE1.8V
}

This is how you tell SignalStorm which type of input goes where.

Hope it helps :).

Ivan

Posted on: 2006/1/25 2:22
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Re: RTL Compiler
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Thanks Ivan! Now I got the multiple voltages set up.

Wei

Posted on: 2006/1/25 15:20
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Re: RTL Compiler script and constraints
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I've uploaded a basic script and constraints file for RTL Compilier. Some of the comments can be removed if one wants to experiment with PLE models, clock-gating cells from the library, TCF/SAIF-based optimizations, and retiming. These are advanced topics not really needed for a basic compile.

Nick

Attach file:


txt rtl-compiler-script.txt Size: 6.61 KB; Hits: 3943
txt rtl-compiler-constraints.g.txt Size: 4.42 KB; Hits: 1373

Posted on: 2006/1/27 11:52
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Re: RTL Compiler script and constraints
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Hi Nick,

Ahh, the trusty good old DTMF chip
Unbelievable how much milage we have gotten out of that good old design.

Thanks,
Johannes

Posted on: 2006/1/27 11:56
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Re: RTL Compiler script and constraints
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Hi Guys,
Can you please help me regarding the generated clock in RTL Compiler

means i want to generate a clock from system clock...when i defined it it is giving error as Pin defined is not found in the inner module.
Please help me,i need it urgently.
Achiranshu

Posted on: 2008/6/4 1:43
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