Hello everyone,
I just started using rc for synthesis and i keep getting awful results after the optimization process.for example rc does not insert any buffers in clock nets or all of the inputs resulting in outrageous delays and slack.as i do not have any previous experience in synthesis procedures,and all the tutorials i found were elementary,i woyld appreciate any suggestions for writing tcl scripts.

Quote:

Hi,

Usually synthesis tools operate on ideal clocks that meaning no delay in a clock path from a clock source to the leaf cells.

It leads in no optimization on clock paths.
Buffers insertion could appear in case when clock path violates for some kind of constraint. For example, it is max fanout, transition time, capacitance or for another reason.

Buffer insertion on clock nets is typically done during clock tree synthesis, but it should be in backend tools.