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Cadence Verilog AMS Simulation 'GCC' Error
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Hello all
I am trying to learn how to run verilog AMS simulations in cadence. We
have IC5141 and IUS810. I need to learn and give a demo to other
students. I found a tutorial which walk you through simulating the
Analog Equalizer given in the sample VFS_PHY_180 library provided by
cadence. It is based on the Cadence Verilog AMS simulation guide.
However I get the following error. I also get the same error running a
simple ideal ADC example. I have all systemc folders in path and it
shows GCC 3.2.3 and GCC 4.1 install. Do I need to some how install GCC
3.3 inside cadence directory. Please help.
Elaborating VFS_AMS_PHY180_sims.aeq_ac_sim:config_ams -
ncelab VFS_AMS_PHY180_sims.aeq_ac_sim:config_ams -snapshot
aeq_ac_sim:ams1224728805594 -cdslib
/home/users/vaibhav/adc_class/cds.lib -propsPath
/home/users/vaibhav/adc_class/vfs_amsflow/VFS_AMS_PHY180_sims/
aeq_ac_sim/config_ams/prop.cfg -hdlvar
/home/users/vaibhav/adc_class/vfs_amsflow/hdl.var
VFS_AMS_PHY180_sims.cds_globals:aeq_ac_sim_config_ams
ConnRules_18V_mid -errormax 50 -discipline logic -timescale 1ns/1ns -
noparamerr -use5x4vhdl -status -delay_mode None
-novitalaccl -update -omicheckinglevel Standard -access +r-w-c -
modelpath
"/home/users/vaibhav/adc_class/vfs_amsflow/spectre_models/
gpdk.scs(NN)"
ncelab: 08.10-s004: (c) Copyright 1995-2008 Cadence Design Systems,
Inc.
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
ncelab: *F,INTERR: INTERNAL ERROR
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncelab 08.10-s004
HOSTNAME: lnx1.cnel.ufl.edu
OPERATING SYSTEM: Linux 2.6.9-67.EL #1 Wed Nov 7 13:41:13 EST 2007
i686
MESSAGE: Failed to open Spectre Simulation Image Generation library
with error: /cds/ic5141/tools/lib/libgcc_s.so.1: version
`GCC_3.3' not found (required by /cds/ius810/./tools.lnx86/systemc/gcc/
4.1/install/lib/libstdc++.so.6)

Posted on: 2008/10/27 5:35
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Re: Cadence Verilog AMS Simulation 'GCC' Error
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vaibhavgar,
your idea sounds very good, but I'm sorry I can't help with this 'cos I'm not really knowledgeable about this matter.
Good luck
[color=#EEEEEE]simulation credit auto[/color]

Posted on: 2009/5/18 22:51
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Re: Cadence Verilog AMS Simulation 'GCC' Error
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interesting.. im going to check this one out..
simulation assurance vie

Posted on: 2009/5/23 19:30
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Re: Cadence Verilog AMS Simulation 'GCC' Error
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It's helful. Thanks a lot



[color=#EEEEEE]simulationcredit[/color]

Posted on: 2009/5/31 17:35
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Re: Cadence Verilog AMS Simulation 'GCC' Error
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I'm not really knowledgeable about this matter.
[color=#CCCCCC]sonnerie portable gratuite[/color]

Posted on: 2009/6/30 17:29
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Re: Cadence Verilog AMS Simulation 'GCC' Error
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thanks for this one..

commission de surendettement

Posted on: 2009/7/22 13:27
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