I am a newbie in ASIC design and I do not have much experience in working with design kits. I am currently trying to tape out a chip but working with the tools are having me a hard time. So as a simple exercise I decided to make a chip with single inverter and go through all the steps at once. I have IC 6.1 and Assura installed (+ Hspice ...). My design is targeting IBM 9flp (90nm) technology and I have the design kit integrated into the CIW.

Now, I am about to layout the inverter in the Layout Editor tool but I noticed that there are so many different layers which makes me so confused. For instance for the first metal layer (M1), there are M1-gd, vd, os, ls, pn, ll, vp, on layers (similar variants for other metal layers).

I was wondering what is the difference between these variants/layers? Is there any documentation from IBM for these layers? Could someone give me some insight?

Thanks,
Mehrdad