Synopsys Pathmill

This is a quick getting-started guide for Synopsys Pathmill. This tool performs device level static timing analysis and fits into a custom digital flow. For a standard-cell based flow there are better tools available, most notably Synopsys Primetime and Cadence First Encounter timing analysis. Pathmill is most often used for timing analysis of circuits in domino logic or other high speed custom digital logic.

Overview

The following files are used in this tutorial:

• adder8.sp: The circuit netlist
• adder8.cfg: The pathmill configuration file

Running Pathmill

Running pathmill is fairly straight forward. All that is required is a SPICE netlist of the circuit, typically extracted from a layout or generated from a schematic. The second input is a config file that sets a number of pathmill variables. Most importantly, it specifies the inputs and outputs of the circuit. Pathmill will start path searching at the inputs and continue until it hits an output.

To run Pathmill do:

pathmill -c adder8.cfg -n adder8.sp

We instructed Pathmill to find the 50 longest paths. The window will look similar to this:

Reading the Results

The results are written to the file "pathmill.out". The data looks similar to a timing report from Primtetime, only it is on the device level, not the gate level.

Open the results file in a text editor, e.g. using "emacs pathmill.out". It should look as follows:

We see that the longest path in this design starts at "cin" and ends at "cout". It has a delay of 1.555ns. Further down in the file Pathmill actually provides a detailed report for each of the 50 most critical paths.

Pathmill is a fast-Spice tool, that means it performs a number of optimizations and simplifications to achieve almost SPICE-like accuracy at a fraction of the time. The config file has a number of entries where the level of accuracy can be adjusted.